The design and implementation of an electronic sign pattern display

• <p> </p><p><b>LIST OF FIGURES</b></p><p>Fig. 3.1: Block Diagram of a Dynamic Sign Display </p><p>Fig. 3.2: Arrangement of the Pattern Display </p><p>Fig. 4.1: Transformer Arrangement </p><p>Fig. 4.2: Bridge Rectifier </p><p>Fig. 4.3: Voltage and Current Waveforms</p><p>Fig. 4.4: Full Diagrams of Power Supply </p><p>Fig. 5.1: Four Bit Series in Parallel out Register Logic Circuit Arrangement</p><p>Fig. 5.2: Clear and Shift Sequence</p><p>Fig. 5.3: Circuit Diagram &nbsp;for SR Ftip-Flop </p><p>Fig. 5.4: Timing Diagram for SR Ftip-Flop Unclocked</p><p>Fig. 4.4.B: Clocke Circuit</p><p>Fig. 6.1: Transistor Switch/Relay Drive</p><p>Fig. 6.2: Wave form of a Monostable, Fti-Flop</p><p>Fig. 7.1: Astable Multivibrator </p><p>Fig. 7.2: Internal Block Diagram of CMOS555 Timer</p><p>Fig. 7.3: 555CMOS Connection as a Multivibrator </p><p>Fig. 7.4: 555CMOS Connection as a Timer</p><p>Fig. 7.5: 555CMOS Connection as a Monostable Vibrator </p><p>Fig. 8.1: Asynchroneous Decade Counter using Reset </p><p>Fig. 8.2: Asynchroneous Decade Using Feedback</p><p>Fig. 8.3: Timing Wave form</p><p>Fig. 8.4: Pin configuration of Latch Counter</p><p>Fig. 8.5: Circuit Diagrams of a Divided Counter </p><p>Fig. 8.6: Complete Circuit Diagram of Electronics Sign Post</p><p>Fig. 8.7: Complete Picture of Electronic Sign Post &nbsp;</p><p><b>TABLE OF CONTENTS</b></p><p>Title Page </p><p>Declaration </p><p>Approval Page</p><p>Dedication </p><p>Acknowledgements</p><p>List of Table </p><p>List of Figure </p><p>Table of Contents </p><p>Abstract </p><p>Description/Functions of Components Used with </p><p>List of Figures</p><p><b>

Chapter ONE

INTRODUCTION

• </b></p><p>Introduction </p><p><b>

Chapter TWO

LITERATURE REVIEW

• </b>&nbsp;</p><p>Literature review</p><p><b>

Chapter THREE

SYSTEM DESIGN AND IMPLEMENTATION

• </b></p><p>Methodology </p><p><b>

Chapter FOUR

SYSTEM TESTING AND EVALUATION

• </b></p><p>Power supply</p><p>Rectification </p><p>Filtration </p><p><b>

Chapter FIVE

SUMMARY, CONCLUSION AND RECOMMENDATIONS

• </b></p><p>Design of sequential Counter </p><p><b>CHAPTER SIX</b>&nbsp;</p><p>Design of the transistor/Relay Drive </p><p><b>CHAPTER SEVEN</b>&nbsp;</p><p>Design of system timing circuit </p><p>Design of an interated timing circuit </p><p>Astable multivbrator </p><p>Asignchronous counter </p><p>Synchronous counter</p><p><b>CHAPTER EIGHT </b></p><p>Construction and packaging </p><p>Packaging </p><p>Problem encountered and solutions </p><p><b>References </b></p> <br><p></p>