Thesis Abstract

The Space Plug-and-play Interface Simulation Equipment (SPISE) box was developed by ÅAC to aid in the debugging of satellite modules. This report covers the analysis and conversion of this box to provide initial support for the Space Plug-and-play Avionics (SPA) set of protocols in a single Field Programmable Gate Array (FPGA).

A major part of this conversion is the design of SPA-U support for which both a host and slave Universal Serial Bus 1.1 (USB 1.1) stack is needed. The comparison of methods to get this functionality and the final design of the Intellectual Property (IP) cores which are implemented in the Very High Speed Integrated Circuit Hardware Description Language (VHDL) language utilizing the freely available from OpenCores, USBHostSlave controller IP by Steve Fielding.

The intended target hardware for this project is the reuse of the existing platform, an Actel A3P1000 FPGA containing one million gates. Described in this report are the necessary choices made to implement support for the SPA protocols within a limited time and budget while maintaining compatibility with the architecture of the SPISE box.

Thesis Overview